The present invention relates, in general, to the field of electronic product testing. More particularly, the present invention relates to techniques useful in the validation of electronic hardware diagnostics and redundant hardware utilizing boundary scan cells as defined by the Institute of Electrical and Electronics Engineers ("IEEE") Standard Test Access Port and Boundary Scan Architecture, IEEE Standard 1149.1-1990 promulgated in response to the industry Joint Test Action Group ("JTAG").
With the trend towards ever more densely populated integrated circuit boards and more highly integrated components, the problems attendant test, validation of design and verification of functionality become more complex. To ensure that a particular product performs to specification, it is generally necessary to inject faults or errors into the system to simulate a potential field problem and determine if system diagnostics detect the problem and respond properly by, for example, switching-in redundant hardware to take over the functionality of the failed board or component.
Currently, testing procedures have involved the connection of logic analyzers, emulators and other test or fault injecting equipment by means of hardware probes through jumper wires, robotic arms or test fixtures such as "bed-of-nails" testers. At the component level, as circuit functionality becomes increasingly integrated in silicon, the capability of isolating and physically accessing particular elements of a given component becomes extremely difficult if not impossible. Moreover, with the advent of surface mount technologies, test and validation procedures at the board level become even more problematic since test nodes must be accessed at the component side and components may be mounted on both sides of the board. Even the use of extender cards to provide physical access to test nodes may prove unsatisfactory due to the possibility that such an extender may cause problems with critical timing requirements.
As a result, the use of physical probing to detect system faults has been recognized by the industry as impractical, leading to the formation of JTAG, and culminating in the IEEE-1149.1 standard. The building of devices (whether components or board level systems) to the JTAG specification requires that they have the ability to test themselves through built-in self test ("BIST") by allowing access to nodes and circuits which are otherwise physically inaccessible. This capability is based upon a test access port ("TAP") state machine which allows control and access to a "boundary scan" architecture. To implement the boundary scan architecture the component or board must include boundary scan cells which are implemented between each component pin or board connector and the internal logic circuitry. The boundary scan cells are also connected together forming a shift register path around the periphery of the circuit giving rise to the term boundary scan.
Boundary scan, which is increasingly integrated with more and more components and board level systems, therefore allows the internal logic of a component or board level system to be tested without being physically probed. Significantly, however, the JTAG boundary scan architecture has heretofore been utilized solely to detect existing faults and neither contemplates nor provides a means to intentionally inject them into the product to determine the validation of on-board diagnostics and/or redundant hardware.